Senior Verification Engineer / Team Lead

• Minimum 7-10 years of experience in ASIC/SoC verification, including 3-5 years as an architect or lead

• Proficiency in SystemVerilog/UVM, VHDL/Verilog, C/C++, Python/TCL scripting.

• Proven experience in team management and leading technical projects

• Strong understanding of SoC architectures and communication protocols (AXI, AHB, PCIe, Ethernet...)

• Leadership, ability to bring a team together, and excellent communication skills

• Education: Master's degree or PhD in electronics, microelectronics, embedded computing, or equivalent

• Languages: Fluent French and professional English (reading, writing, speaking).

• Formal verification methodologies, assertions (SVA)

• Simulation tools (Synopsys VCS, Cadence Xcelium, Mentor Questa)

• Participation in cutting-edge innovative projects in an international environment.

Dear candidate, even if you consider you do not fulfill all the qualifications mentioned above, please still apply and share with us why you believe you would be a good fit.

• Benefits: annual bonus*; meal vouchers (60% covered by SiPearl); health insurance (70% covered by SiPearl); illimited access and pre-paid sessions with a practitioner of your choice on our mental health partner app, moka.care; technical, linguistic and personal development training; BSPCE

• ⚠️ Please note that while we do not provide VISA Sponsorship, we are committed to assisting international candidates with the visa application process to the best of our ability.

❓ About SiPearl...

SiPearl is the European fabless designer of sovereign secure high-performance energy-efficient CPUs for HPC, AI and data centres. These CPUs will help address strategic challenges in the fields of security, defence, medical research, energy, climate and engineering with a reduced environmental footprint.

In June 25, SiPearl completed the design of the most complex CPU ever designed in Europe, Rhea1. Featuring 80 Arm Neoverse V1 cores, with 61 billion transistors, it is currently in production at TSMC. Sipearl CPUs will equip the two first European exascale supercomputers belonging to EuroHPC JU: Rhea1 will be integrated into the JUPITER machine based in Germany and Rhea2 will be part of Alice Recoque in France.

Incubated within the European Processor Initiative (EPI) consortium and seed-funded by the European Union, SiPearl employs almost 200 people in :

• France (Maisons-Laffitte, Grenoble, Massy, Sophia Antipolis),

• Spain (Barcelona)

• and Italy (Bologna)

Following a €130 million Series A, the company has launched its Series B round.

💻 About the role

In this role, you will work closely with our Verification Team Lead to define and drive the architecture of SiPearl's microprocessor verification platform. You will play a key role in designing and validating our next-generation SoCs while leading a team of engineers.

• Define the verification platform architecture (UVM/SystemVerilog, C/C++, Python...)

• Develop and maintain test environments, verification benches, and functional simulations

• Plan, prioritize, and track verification activities throughout the development cycle

• Lead and mentor a team of verification engineers

• Collaborate with system architects, design teams, and embedded software teams.

• Contract: Permanent Contract

• Work model: On-Site or Hybrid (2 days/week remote)

• 📍 Office: This role is open for our locations in France (Maisons-Laffitte, Massy, Grenoble and Sophia Antipolis), Spain (Castelldelfels - Barcelona), Italy (Bologna)