Emulation-Prototyping Senior Engineer

• At least 5 years of past experience developing in SoC Design and delivering hardware products or solutions

• HDL and HVL Languages (Verilog, System Verilog, C/C++, SystemC, VHDL)

• Familiarity with UVM methodology and Testbench construction, Functional Coverage and Verilog Assertions, Verification IPs

• EDA Tools for digital simulation (Questa, VCS, Xcelium) and Debug (Visualizer, Verdi, Verisium)

• Familiarity with System / Functional Modeling Languages (C,C++, SystemC TLM LT/AT)

• Direct experience in constructing virtual platforms for SW development, architectural exploration, co-emulation. Experience with Commercial Virtual Prototyping platforms (Synopsys Platform Architect, Virtualizer or Cadence Helium or Siemens NextGen/Vista) or other opensource frameworks like Gem5

• Excellent communication skills

• MS in EE, CE, CS or a related technical discipline

• Direct Experience with Commercial Emulation Platforms (Synopsys Zebu EP1/2, Cadence Palladium Z1/Z2, Siemens Veloce Strato+) or Prototyping Platforms (Synopsys HAPS-80/100, Cadence Protium X1/X2, Siemens Primo, Primo CS, ProFPGA, ProFPGA CS) is appreciated

• Direct experience in developing/setting-up custom or commercial transactors for interfacing System Verilog UVM Testbench or SystemC TLM Virtual Platforms with Emulation platforms is appreciated

• Direct experience setting-up Emulation and prototyping platforms for SW debug through physical or virtual JTAG interface is appreciated

• Experience in Processors Compliance Testing, ISS simulators & reference models (Spike, riscvOVPsim), Stress Tests, Benchmarking and other commercial processor centric functional verification siutes (Sting, ImperasDV) is appreciated

• Familiarity with high performance coherent on-chip & chiplet to chiplet communication protocols (AXI-ACE, CHI, CXL), interfaces (PCIe, UCIe), debug interfaces/protocols (JTAG, ATB, TPIU etc...) cache coherency, interfaces to High Performance Memory Systems (HBM controller/PHY) is appreciated

• Experience with RISC-V toolchain and ISA is a plus

We are actively seeking a Silicon Design Framework and Emulation-Prototyping Engineer to join our dynamic and growing Hardware Design team. The mission of the role is to enable fast, reliable, and scalable hardware-software co-design by developing and maintaining design frameworks, emulation platforms, and prototyping environments that accelerate silicon validation and system bring-up.

You will work in synergy with Hardware Validation, Architecture and Software teams to:

• Develop and Implement Emulation & Prototyping strategies based on product goals and KPIs

• Enable Accelerated HW Validation, Compliance testing and Stress Testing using Emulation platforms

• Enable Hardware SW-drivenSoftware Development and Debug on Emulation and Prototyping Platforms

• Contribute to the definition and maintenance of Virtual Platforms for SW development, Co-Emulation (Hybrid platforms), SW-driven HW Verification and Architectural Exploration

• Develop and maintain Emulation, Prototyping and Virtual Prototyping Frameworks to enable the Performance and Power Analysis of the SoC

• The candidate should be equipped with a unique skills-set: Self-starter, self-motivated, humility, excellent communications skills; outstanding human qualities as honesty, integrity, fellowship, generosity and commitment with his/her mission to change the world.

• Excellent communication and management skills

• He/she is a natural team player with the aim to create a positive impact in the society.