DFT ASIC / SoC Engineer | Design for Test

DFT ASIC / SoC Engineer | Design for Test - Grupo Oesía

Our projects become technology that protects, connects and drives strategic sectors: our own. At Grupo Oesía, we work to ensure innovation delivers real impact, and we are looking for people who want to be part of that challenge.

At Cipherbit, part of Grupo Oesía, we are looking for a DFT ASIC / SoC Engineer to contribute to Design for Test activities within the development of complex integrated circuits and SoCs for advanced technology programmes.

You will work on activities related to DFT, ATPG, MBIST and LBIST, contributing to test and silicon validation throughout the ASIC development lifecycle.

You will collaborate closely with multidisciplinary teams specialising in architecture, RTL design, verification, physical implementation, test and silicon validation.

The role offers the opportunity to participate across the complete ASIC lifecycle, including tape-out and fabrication, within strategic projects involving advanced semiconductor and security technologies.

• Participate in Design for Test (DFT) activities for complex ASIC and SoC developments.
• Contribute to activities involving ATPG, MBIST and LBIST.
• Support design-for-test requirements throughout the ASIC development lifecycle.
• Work with complex SoCs based on RISC-V, ARM or equivalent architectures.
• Collaborate on the integration of third-party IPs and complex subsystems.
• Work within Front-End and/or Back-End ASIC flows, collaborating closely with digital design and physical implementation teams.
• Collaborate with verification teams working with advanced UVM methodologies.
• Participate in silicon validation and test activities following tape-out and fabrication.
• Collaborate with multidisciplinary teams covering design, verification, physical implementation and test.

• Degree in Telecommunications Engineering, Electronics, Industrial Engineering, Computer Engineering or another relevant engineering discipline.
• Professional experience within ASIC and/or complex SoC development environments.
• Experience in DFT, ATPG, MBIST/LBIST and silicon validation.
• Participation in one or more complete ASIC development lifecycles.
• Experience with ASIC tape-outs and integrated circuit fabrication.
• Experience working with complex SoCs based on RISC-V, ARM or equivalent architectures.
• Experience with the integration of third-party IPs and complex subsystems.
• Knowledge of Front-End and/or Back-End ASIC flows.
• Knowledge of advanced verification environments using UVM methodologies.
• Experience using industry-standard EDA environments and tools from Cadence, Synopsys or Siemens EDA.
• Experience working within multidisciplinary teams covering design, verification, physical implementation and test.

• Direct participation in successful ASIC tape-outs.
• Experience working across more than one semiconductor technology node.
• Experience with semiconductor technologies between 22 nm and 65 nm.
• Experience working with complex SoC architectures.
• Previous experience providing technical leadership within ASIC design environments.
• Experience collaborating with foundries, design houses, technology centres and IP providers.