RTL ASIC Engineer

RTL ASIC Engineer | Digital Design & Semiconductor Technologies - Grupo Oesía

Our projects become technology that protects, connects and drives strategic sectors: our own. At Grupo Oesía, we work to ensure innovation delivers real impact, and we are looking for people who want to be part of that challenge.

At Cipherbit, part of Grupo Oesía, we are looking for an RTL ASIC Engineer to contribute to the design and development of complex digital circuits and SoCs within advanced technology programmes.

You will work on RTL design and digital implementation, contributing to complex SoC solutions based on RISC-V, ARM or equivalent architectures and supporting the integration of third-party IPs and subsystems.

You will participate across the ASIC development lifecycle, working closely with architecture, verification, DFT, physical implementation, test and silicon validation teams.

You will join a highly specialised engineering environment focused on microelectronics, advanced semiconductor technologies and security-related solutions.

• Contribute to the RTL design of complex ASIC and SoC solutions.
• Participate in digital designs based on RISC-V, ARM or equivalent architectures.
• Support the integration of third-party IPs and complex digital subsystems.
• Work within Front-End ASIC development flows and collaborate with Back-End and physical implementation teams.
• Work closely with verification engineers in environments using advanced UVM methodologies.
• Collaborate on activities related to DFT, ATPG, MBIST/LBIST and silicon validation.
• Participate in ASIC development activities leading towards tape-out and integrated circuit fabrication.
• Collaborate with multidisciplinary teams covering architecture, RTL design, verification, physical implementation and test.
• Contribute to technical decisions throughout the design and implementation stages of complex integrated circuits.

• Degree in Telecommunications Engineering, Electronics, Industrial Engineering, Computer Engineering or another relevant engineering discipline.
• Professional experience in digital design within ASIC and/or SoC environments.
• Participation in one or more complete ASIC development lifecycles.
• Experience with ASIC tape-outs and integrated circuit fabrication.
• Experience working with complex SoCs based on RISC-V, ARM or equivalent architectures.
• Experience with the integration of third-party IPs and complex subsystems.
• Knowledge of Front-End and/or Back-End ASIC flows.
• Experience working in advanced verification environments using UVM methodologies.
• Knowledge of DFT, ATPG, MBIST/LBIST and silicon validation.
• Experience using industry-standard EDA environments and tools from Cadence, Synopsys or Siemens EDA.
• Experience working within multidisciplinary teams covering design, verification, physical implementation and test.

• Direct participation in successful ASIC tape-outs.
• Experience working across more than one semiconductor technology node.
• Experience with semiconductor technologies between 22 nm and 65 nm.
• Experience contributing to the definition of complex SoC architectures.
• Previous experience providing technical leadership within ASIC design environments.
• Experience collaborating with foundries, design houses, technology centres and IP providers.