Formal Verification Lead

• Competitive package.

As a static formal verification lead, you will play a key role in ensuring functional correctness and low-power intent integrity across the design lifecycle. You will be responsible for equivalence checking with and without UPF, ensuring seamless convergence between RTL, synthesis, and physical design stages for hierarchical designs.

Key Responsibilities

• Perform RTL-to-Gate and Gate-to-Gate equivalence checks using tools like Synopsys

Formality

• Debug LEC failures, including issues arising from clock gating, retention, isolation, and level
  shifters
• Ensure convergence of LEC across synthesis, place-and-route, and ECO cycles
• Work closely with RTL, Synthesis, DFT, and Physical Design teams to resolve design
  mismatches
• Handle ECO validation and ensure equivalence closure post-design changes
• Develop automation scripts and improve methodology for LEC sign-off

Technical Skills

• Bachelor's or Master's degree in Electrical/Electronics Engineering or related discipline
• 7+ years of experience in Formal Verification/LEC
• Strong expertise in tools like Synopsys Formality/VC LP
• Understanding of low-power design concepts (UPF)
• Experience with synthesis, netlist optimizations, and equivalence debugging
• Proficiency in scripting languages such as TCL, Python, or Perl
• Experience with hierarchical Sub system level LEC flows

• 4 days per week in the Barcelona office (city center), 1 day WFH.
• 1 week of work from everywhere in the world.