Senior Power Integrity Engineer

• Competitive package.

You will own the power distribution network from voltage regulator output to die bump - impedance, IR drop, droop and decoupling across package and board. Senior IC role: you own the PDN numbers that power delivery, SI and the package team design against.

• PDN design and closure for a multi-die AI accelerator package

• DC IR, AC impedance, transient droop and electro-thermal analysis across die, package and board

• Decoupling strategy and optimisation across on-die, package and board tiers

• Package-board anti-resonance identification and mitigation

• PDN noise to jitter translation, closed back into the SI budget

• Analysis & closure: Build and close DC IR, electro-thermal, AC impedance and transient PDN analysis from VR output through package to die bump. Set target impedance per rail and hold the design to it.

• Chip power models: Work with CPM and workload current profiles to size on-die, package and board decoupling, and to predict droop across all three droop timescales.

• Resonance & mitigation: Identify package-board anti-resonance and cavity behaviour, and drive the plane, via and decap changes that mitigate it.

• SI coupling: Translate PDN noise into jitter through PHY supply sensitivity, and feed the result back into the channel budget.

• Vendor & validation: Drive CPM and model requirements with IP, PHY and package vendors. Correlate against PDN impedance measurement and on-die droop telemetry, and support bring-up and power debug.

• 4 days per week in the Barcelona office (city center), 1 day WFH.

• 1 week of work from everywhere in the world.